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74ACQ245 * 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
July 1989 Revised March 2005
74ACQ245 * 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
General Description
The ACQ/ACTQ245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for busoriented applications. Current sinking capability is 24 mA at both the A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bidirectional transceiver. Transmit (active-HIGH) enables data from A Ports to B Ports; Receive (active-LOW) enables data from B Ports to A Ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition. The ACQ/ACTQ utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard ACT245
Ordering Code:
Order Number 74ACQ245SC 74ACQ245SJ 74ACQ245PC 74ACTQ245SC 74ACTQ245SJ 74ACTQ245QSC 74ACTQ245MSA 74ACTQ245MTC 74ACTQ245MTCX_NL (Note 1) 74ACTQ245PC Package Number M20B M20D N20A M20B M20D MQA20 MSA20 MTC20 MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS010236
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74ACQ245 * 74ACTQ245
Connection Diagram
Pin Descriptions
Pin Names OE T/R A0-A7 B0-B7 Description Output Enable Input Transmit/Receive Input Side A 3-STATE Inputs or 3-STATE Outputs Side B 3-STATE Inputs or 3-STATE Outputs
Truth Table
Inputs Outputs OE L T/R L H X Bus B Data to Bus A Bus A Data to Bus B HIGH-Z State
Logic Symbols
L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial
IEEE/IEC
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74ACQ245 * 74ACTQ245
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI
0.5V to 7.0V 20 mA 20 mA 0.5V to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r50 mA r50 mA 65qC to 150qC r300 mA
140qC
Recommended Operating Conditions
Supply Voltage (VCC) ACQ ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate 'V/'t ACQ Devices VIN from 30% to 70% of VCC VCC @ 3.0V, 4.5V, 5.5V Minimum Input Edge Rate 'V/'t ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
0.5V VCC 0.5V
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC
DC Input Voltage (VI) DC Output Diode Current (IOK) VO VO
0.5V VCC 0.5V
40qC to 85qC
DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) PDIP
125 mV/ ns
DC Electrical Characteristics for ACQ
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 5) IOLD IOHD ICC (Note 5) IOZT Maximum Input Leakage Current Minimum Dynamic Output Current (Note 4) Maximum Quiescent Supply Current Maximum I/O Leakage Current 5.5 5.5 5.5 5.5 4.0 75 mA mA VOLD VOHD VIN or GND VI (OE) VIL, VIH 1.65V Max 3.85V Min VCC 5.5 0.002 0.001 0.001 TA Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36
25qC
TA
40qC to 85qC
2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4
Guaranteed Limits
Units VOUT V
Conditions 0.1V
or VCC 0.1V VOUT 0.1V
V
or VCC 0.1V
V
IOUT VIN
50 PA
VIL or VIH
2.46 3.76 4.76 0.1 0.1 0.1 V V
IOH IOH IOH IOUT VIN
12 mA 24 mA 24 mA (Note 3)
50 PA VIL or VIH 12 mA 24 mA 24 mA (Note 3) VCC, GND
0.44 0.44 0.44 V
IOL IOL IOL VI
r0.1
r1.0
PA
75
40.0
PA
r0.3
r3.0
PA
VI VO
VCC, GND VCC, GND
3
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74ACQ245 * 74ACTQ245
DC Electrical Characteristics for ACQ
Symbol VOLP VOLV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA Typ 1.1
(Continued)
TA
25qC
40qC to 85qC
Units
Conditions Figure 1, Figure 2 (Note 6)(Note 7) Figure 1, Figure 2 (Note 6)(Note 7) (Note 6)(Note 8) (Note 6)(Note 8)
Guaranteed Limits 1.5 V V V V
0.6
3.1 1.9
1.2
3.5 1.5
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. Note 6: DIP package. Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V; one output @ GND. Note 8: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD), 0V to threshold (VIHD), f 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN IOZT ICCT IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Maximum 3-STATE Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 10) Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 1.1 4.0 1.5 0.6 1.5 75 mA mA mA 5.5 5.5 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36
25qC
TA
40qC to 85qC
2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44
Guaranteed Limits
Units V V V VOUT VOUT IOUT VIN V V IOH IOH IOUT VIN V IOL IOL VI VI VO VI VOLD
Conditions 0.1V 0.1V
or VCC 0.1V or VCC 0.1V
50 PA
VIL or VIH
24 mA 24 mA (Note 9)
50 PA VIL or VIH 24 mA 24 mA (Note 9) VCC, GND VIL, V IH VCC, GND VCC 2.1V 1.65V Max 3.85V Min VCC or GND
r0.1 r0.3
r1.0 r3.0
PA PA
75
40.0
VOHD VIN
PA
V V V V
Figure 1, Figure 2 (Note 11)(Note 12) Figure 1, Figure 2 (Note 11)(Note 12) (Note 11)(Note 13) (Note 11)(Note 13)
0.6
1.9 1.2
1.2
2.2 0.8
Note 9: All outputs loaded; thresholds on input associated with output under test. Note 10: Maximum test duration 2.0 ms, one output loaded at a time. Note 11: DIP package. Note 12: Max number of outputs defined as (n). n1 Data Inputs are driven 0V to 3V; one output @ GND. Note 13: Max number of Data Inputs (n) switching. (n1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD) f 1 MHz.
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74ACQ245 * 74ACTQ245
AC Electrical Characteristics for ACQ
VCC Symbol tPHL tPLH tPZL tPZH tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 15) Data to Output
Voltage Range 3.3 is 3.3V r 0.3V Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
TA CL Min 2.0 1.5 3.0 2.0 1.0 1.0
25qC
50 pF Typ 7.5 5.0 8.5 6.0 8.5 7.5 1.0 0.5 Max 10.0 6.5 13.0 8.5 14.5 9.5 1.5 1.0
TA
40qC to 85qC
CL 50 pF Max 10.5 7.0 13.5 9.0 15.0 10.0 1.5 1.0 ns ns ns ns Units
Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time
(V) (Note 14) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Min 2.0 1.5 3.0 2.0 1.0 1.0
Note 14: Voltage Range 5.0 is 5.0V r 0.5V
AC Electrical Characteristics for ACTQ
VCC Symbol tPHL tPLH tPZL, tPZH tPHZ, tPLZ tOSHL tOSLH Parameter Propagation Delay Data to Output Output Enable Time Output Disable Time Output to Output Skew (Note 17) Data to Output 5.0 5.0 5.0 2.0 1.0 7.0 8.0 0.5 9.0 10.0 1.0 2.0 1.0 9.5 10.5 1.0 ns ns ns (V) (Note 16) 5.0 Min 1.5 TA CL
25qC
50 pF Typ 5.5 Max 7.0
TA
40qC to 85qC
CL 50 pF Max 7.5 ns Units
Min 1.5
Note 16: Voltage Range 5.0 is 5.0V r 0.5V Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Capacitance
Symbol CIN CI/O CPD Parameter Input Capacitance Input/Output Capacitance Power Dissipation Capacitance Typ 4.5 15 80.0 Units pF pF pF VCC VCC VCC OPEN 5.0V 5.0V Conditions
5
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74ACQ245 * 74ACTQ245
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical to the accuracy and repeatability of the tests. The following is a brief description of the setup used to measure the noise characteristics of FACT. Equipment: Hewlett Packard Model 8180A Word Generator PC-163A Test Fixture Tektronics Model 7854 Oscilloscope Procedure: 1. Verify Test Fixture Loading: Standard Load 50 pF, 500:. 2. Deskew the HFS generator so that no two channels have greater than 150 ps skew between them. This requires that the oscilloscope be deskewed first. It is important to deskew the HFS generator channels before testing. This will ensure that the outputs switch simultaneously. 3. Terminate all inputs and outputs to ensure proper loading of the outputs and that the input levels are at the correct voltage. 4. Set the HFS generator to toggle all but one output at a frequency of 1 MHz. Greater frequencies will increase DUT heating and effect the results of the measurement. 5. Set the HFS generator input levels at 0V LOW and 3V HIGH for ACT devices and 0V LOW and 5V HIGH for AC devices. Verify levels with an oscilloscope. VOLP/VOLV and VOHP/VOHV: * Determine the quiet output pin that demonstrates the greatest noise levels. The worst case pin will usually be the furthest from the ground pin. Monitor the output voltages using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * Measure VOLP and VOLV on the quiet output during the worst case transition for active and enable Measure VOHP and VOHV on the quiet output during the worst case active and enable transition. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements. VILD and VIHD: * Monitor one of the switching outputs using a 50: coaxial cable plugged into a standard SMB type connector on the test fixture. Do not use an active FET probe. * First increase the input LOW voltage level, VIL, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input LOW voltage level at which oscillation occurs is defined as VILD. * Next decrease the input HIGH voltage level, VIH, until the output begins to oscillate or steps out a min of 2 ns. Oscillation is defined as noise on the output LOW level that exceeds VIL limits, or on output HIGH levels that exceed VIH limits. The input HIGH voltage level at which oscillation occurs is defined as VIHD. * Verify that the GND reference recorded on the oscilloscope has not drifted to ensure the accuracy and repeatability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 18: VOHV and VOLP are measured with respect to ground reference. Note 19: Input pulses have the following characteristics: f 3 ns, tf 3 ns, skew 150 ps. 1 MHz, tr
FIGURE 2. Simultaneous Switching Test Circuit
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74ACQ245 * 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
7
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74ACQ245 * 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74ACQ245 * 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Package Number MQA20
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide Package Number MSA20
9
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74ACQ245 * 74ACTQ245
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74ACQ245 * 74ACTQ245 Quiet Series Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 11 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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